A magnetic memory element in a magnetoresistive random access memory (MRAM) semiconductor device has a structure that includes ferromagnetic layers separated by a non-magnetic layer. Information is stored as directions of magnetization vectors in the magnetic layers. The resistance between the magnetic layers depends on the relative orientation of their magnetization directions (magnetic moments). For example, magnetic vectors in one magnetic layer (the xe2x80x9chardxe2x80x9d layer) can be magnetically fixed or pinned, while the magnetic vectors of the other magnetic layer (the xe2x80x9csoftxe2x80x9d layer) are not fixed and are free to switch, e.g., the magnetic moment of the soft layer can be reversed by application of a small magnetic field in operation of the device. Thus, the MRAM device can operate as a memory storage element or cell wherein the magnetic moments of the two magnetic layers are aligned either parallel to one another or antiparallel to one another. In response to the shifting magnetic states, the magnetic memory element represents two different resistances or potentials, which are read by the memory circuit as either a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d It is the detection of these resistance or potential differences that allows the MRAM to read and write information.
Because MRAM elements rely on layers of ferronagnetic film to store information, and the ability to change the alignment of the magnetic layers within the memory bit structure is the primary means of storing and accessing data in the MRAM, the quality of the thin layers of this structure is critical to the performance of this type of device.
An MRAM device integrates magnetic memory elements and other circuits, such as a control circuit for magnetic memory elements, comparators for detecting states in a magnetic memory element, input/output circuits, and the like. These circuits can be fabricated by Complementary Metal Oxide Semiconductor (CMOS) technology that involves many manufacturing steps to form the electric circuitry which typically consists of n-channel and p-channel transistors and active and ppssive circuit elements. The CMOS process requires high temperature steps that exceed 300xc2x0 C. for depositing dielectric and metal layers, and annealing implants, for example.
However, magnetic layers employ magnetic materials that require processing below 300xc2x0 C. in order to prevent detrimental intermixing of the materials that would occur if higher temperatures are employed. In particular, a structure with magnetic layers that have interdiffused has a much reduced capability to shift the magnetic alignment of the magnetic structure. Therefore, the ferromagnetic magnetic layers are usually deposited at a different stage, after formation of the transistors and initial metal layers and circuitry by CMOS processing.
Magnetic memory elements also contain components that, detrimentally, are easily oxidized and are sensitive to corrosion. For example, oxygen contamination of the magnetic layers can pin the magnetic dipoles, not allowing the realignment of the magnetic layers. Therefore, magnetic layers that have been contaminated with oxygen will not perform properly and eventually will corrode.
Accordingly, there is a need for a method of making a magnetoresistive random access memory device that solves the foregoing problems.
The invention provides a low temperature process for depositing silicon nitride or silicon dioxide dielectric films over magnetically active materials in the manufacture of MRAM devices. In particular, the low temperature process is a plasma enhanced chemical vapor deposition (PECVD) at temperatures that are below the standard PECVD process temperature of approximately 400xc2x0 C. to 500xc2x0 C. for deposition of these types of films. More particularly, the dielectric films are deposited at a temperature of about 200xc2x0 C. to 300xc2x0 C., preferably about 225xc2x0 C. to 295xc2x0 C., more preferably about 250xc2x0 C. to 290xc2x0 C. and, especially, 295xc2x0 C. Employing PECVD at a much lower temperature than the high standard PECVD process temperature for deposition of dielectric films eliminates the negative impact of high temperatures on the magnetic properties of the magnetoresistive storage elements.
The invention also provides the use of a low temperature silicon nitride dielectric film proximate to the magnetically active materials. The use of silicon nitride film has the advantage that it is a reducing material and, by virtue of this property, can prevent degradation of the magnetic films that would take place due to the presence of any residual oxygen or moisture from the manufacturing process. Therefore, the MRAM devices produced by embodiments of the invention method preferably comprise silicon nitride dielectric layers comprising about 35% to about 40% by volume of Si, about 35% to about 45% by volume of N, and about 15% to about 30% by volume of H.
The invention provides a magnetoresistive random access memory device with improved magnetic properties including, but not limited to, an improved GMR (Giant Magnetoresistance) effect, more uniform write/read thresholds, and containing a higher percentage of functional memory bits. For purposes of this disclosure, the term xe2x80x9cimproved GMR effectxe2x80x9d means a higher GMR signal indicating a change in resistance for the aligned and unaligned states of the soft magnetic layer of the MRAM device. The MRAM device is produced by a process in which active circuit elements, such as magnetoresistive memory storage bits, are added to semiconductor substrates that already comprise transistors and other circuitry formed by high temperature processes, such as CMOS or the like.
In order to prevent interdiffiusion of the magnetic layers, the magnetoresistive storage material is deposited on a finely planarized initial dielectric layer overlying the semiconductor substrate at a temperature of 300xc2x0 C. or less, preferably 200xc2x0 C. or less, more preferably 100xc2x0 C. or less and, most preferably about 50xc2x0 C. Following deposition of the magnetic layers, each further step in the process requiring deposition of a layer of metal or of dielectric material is performed at a temperature that preferably does not exceed 300xc2x0 C. and, more preferably, does not exceed 295xc2x0 C. That is, the deposition temperature can be about 200xc2x0 C. to 300xc2x0 C., preferably about 225xc2x0 C. to 295xc2x0 C., more preferably about 250xc2x0 C. to 290xc2x0 C. and, especially, 295xc2x0 C.
In particular, deposition of dielectric layers, after the magnetoresistive storage layers are applied, is by a plasma enhanced chemical vapor deposition (PECVD) process in which parameters such as, but not limited to, the percentage of low radio frequency, the pressure, and the like, have been altered from the standard process, in order to produce dielectric film layers with suitable thickness, uniformity, chemical composition, and minimal surface defects.
Thus, the invention provides a magnetoresistive random access memory device (having improved properties) produced by a process comprising the steps of forming an initial dielectric layer overlying a semiconductor substrate; planarizing the initial dielectric layer; depositing one or more layers of magnetoresistive storage material on the initial dielectric layer at a temperature of, most preferably, about 100xc2x0 C. or less; forming an electrically-conductive stop layer overlying the magnetoresistive storage material layer; forming a hardmask layer overlying the stop layer, wherein the stop layer and the hardmask layer are deposited at a temperature of about 100xc2x0 C. to 300xc2x0 C., preferably about 150xc2x0 C. to about 250xc2x0 C., more preferably about 200xc2x0 C.; etching the stop layer and hardmask layer; patterning the magnetoresistive storage material; forming a dielectric layer overlying the magnetoresistive storage material, wherein the dielectric layer comprises silicon nitride deposited at a temperature of about 200xc2x0 C. to 300xc2x0 C.; forming an electrically-conductive metal layer overlying the dielectric layer; forming a passivation dielectric layer overlying exposed deposited layers, wherein the dielectric layer comprises silicon nitride deposited at a temperature of about 200xc2x0 C. to 300xc2x0 C.; and annealing the device.